CS6720 F 2003
ASSN9
Due Mon, Oct. 27

For the following address trace (all addresses in DECIMAL):

 1 4 8 5 20 17 19 56 9 11 4 43 5 6 9 17 10 21 42 4

Assume the cache is word-addressable.
Assume the contents of the cache is initially empty.
Assume the accesses are all READS (IFETCH, load instruction).

[A] Show the contents of the cache after the accesses in the address trace.
    How many misses of type compulsory? capacity? collision?
    What is the hit rate?
[B] Run the same address trace w/ the cache status as at the end of [A].
    Show the contents of the cache after the accesses in the address trace.
    How many misses of type compulsory? capacity? collision?
    What is the hit rate?

1. The cache is direct mapped w/ 1-word entries.  Total data size is 16 words.

2. The cache is direct mapped w/ 2-word entries.  Total data size is 16 words.

3. The cache is 2-way set associative w/ 1-word entries.
   Total data size is 16 words.